Last week, Christian from Bielefeld University attended the RISC-V Summit Europe 2026 in Bologna, Italy.
Within the workshop on “Advancing RISC-V Adoption in HPC and Cloud Environments“, organized by CAPE’s sibling EU-project HIGHER Project, Christian gave some insights from CAPE’s work regarding RISC-V architectures.
The RISC-V related work in CAPE is based on developing a RISC-V compute module and mapping a RISC-V-based compute clusters on FPGA SoCs. See the presentation slides for more details
